| 專利摘要 | A capacitor array (10, 100, 110) with staggered-layer structure includes a plurality of capacitor units. Each of the plurality of capacitor units comprises a plurality of odd layers (101) formed with a first slot (105); a first via (V1) formed in the first slot (105); a plurality of first connecting portion (103) configured to connect the first via (V1) and the plurality of odd layers (101); a plurality of even layers (102) formed with a second slot (105); a second via (V2) formed in the second slot (105); a plurality of second connecting portion (104) configured to connect the second via (V2) and the plurality of even layers (102); wherein one of the plurality of odd layers (101) is adjacent to one of the plurality of even layers (102) to form a staggered-layer structure. The capacitor unit with staggered-layer structure provides is applicable for CMOS process to be utilized as a power source trace as well as density cell to satisfy design rule for metal density. A plurality of the capacitor units may be coupled and arranged to be the capacitor array adapted to at least one of alignment, non-alignment, overlapping and non-overlapping designs. Moreover, the capacitor array with staggered-layer structure provides characteristics of wide bandwidth, smooth and low impedance, and low conduction loss for bypass capacitor design, which is suitable for power source trance for millimeter wave frequency band. |